The present invention generally relates to a microcomputer system which includes a bus master, a memory and peripheral function units, and buses connected to these units for transferring data among them. More specifically, the present invention is related to a bus operating method for transferring and fetching data among these units.
In a microcomputer system constructed of a processor such as a microcomputer functioning as a bus master, a memory and peripheral functional units, and buses, the data transfer/fetch operations must be carried out among these units.
On one hand, to operate a logic circuit such as a microcomputer at a high speed, there are a first method for operating the logic circuit at the high speed by increasing the operation frequency, and a second method for effectively realizing a high-speed operation by a pipeline process.
In accordance with the first method, there is a limitation in view of device, and generally speaking, cost of the overall system becomes expensive. Thus, normally, the first method is combined with the second method within a balanceable range between cost and performance.
On the other hand, the CISC (complex instruction set computer) system containing a variety of instructions with high performance, and the RISC (reduced instruction set computer) system for executing simple instructions at high speeds are known as the microcomputer system.
In the microcomputer according to the RISC method, a large number of instructions are executed in 1 clock cycle at a high speed by the pipeline-mode execution.
However, in the microcomputer according to the RISC method, frequencies of instruction fetch and of data fetch are high, and then the operation frequency band of the bus control circuit for transferring and fetching the data among the memory and the peripheral function units, may greatly influence performance of the overall system. As a consequence, in such a system with employment of a microcomputer by way of the RISC method, a high-speed bus transfer is required and thus, memories and peripheral function units which can be operated at high speeds are necessarily required. However, actually, all of the memories and peripheral function units connected to this highspeed bus cannot be always operated at the same highspeed as the microcomputer functioning as the bus master for this system. This is because in the specifically highspeed-designed microcomputer, the internal operation is performed in a pipeline mode, and time allowed to one of pipeline stages is equal to only 1 time period of the basic clock employed in this microcomputer system.
When the microcomputer is operated in such a manner at the maximum speed, the internal pipelines are sequentially executed without occurrences of disturbance, and it is extremely difficult that the buses connected to it, and all of the memories as well as peripheral function units are operated without any delay within 1 time period of the basic clock for this system. As a consequence, such an external interface must be provided within the microcomputer, and this external interface performs controls related to various access cycles and various access data sizes in order to execute various access operations on the buses of this system in conjunction with the pipeline control circuit.
As described above, according to the above-mentioned prior art, there is a first problem such that performance of the overall system is determined by the operation speed of bus, and the operation speeds of memories and also peripheral function units, which are accessed by this bus, namely the access time to read or write data.
Also, according to the above-explained prior art, since the bus is controlled by the external interface in conformity to the internal pipeline operation of the microcomputer, another interface corresponding to accesses by all memories and peripheral function units, which may be potentially connected to this bus, must be employed in addition to the originally required external interface. As a result, there is a second problem that the external interface becomes complex and the logic scale would be increased.
Furthermore, there is a third problem that when another system is built by using this microcomputer, the bus interface specifications of this system are restricted. There is a fourth problem that in such a system with having a plurality of bus masters, external interface circuits corresponding to the pipeline operations within the respective bus masters are required, the quantity of which is equal to that of the bus masters.